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NXP Semiconductors
PCA9633
4-bit Fm+ I 2 C-bus LED driver
Table 9. MODE2 - Mode register 2 (address 01h) bit description …continued
Legend: * default value.
Bit
1 to 0
Symbol
OUTNE[1:0]
[3][4]
Access
R/W
Value
00
01*
Description
When OE = 1 (output drivers not enabled), LEDn = 0.
When OE = 1 (output drivers not enabled):
LEDn = 1 when OUTDRV = 1
LEDn = high-impedance when OUTDRV = 0 (same as OUTNE[1:0] = 10)
10
11
When OE = 1 (output drivers not enabled), LEDn = high-impedance.
reserved
[1]
[2]
[3]
[4]
See Section 7.7 “Using the PCA9633 with and without external drivers” for more details. Normal LEDs can be driven directly in either
mode. Some newer LEDs include integrated Zener diodes to limit voltage transients, reduce EMI and protect the LEDs, and these must
be driven only in the open-drain mode to prevent overheating the IC.
Change of the outputs at the STOP command allows synchronizing outputs of more than one PCA9633. Applicable to registers from
02h (PWM0) to 08h (LEDOUT) only.
See Section 7.4 “Activ e LOW output enable input” for more details.
OUTNE[1:0] is only for PCA9633 16-pin version.
7.3.3 PWM registers 0 to 3, PWMx — Individual brightness control registers
Table 10. PWM0 to PWM3 - PWM registers 0 to 3 (address 02h to 05h) bit description
Legend: * default value.
Address
Register Bit
Symbol
Access Value
Description
02h
03h
04h
05h
PWM0
PWM1
PWM2
PWM3
7:0
7:0
7:0
7:0
IDC0[7:0]
IDC1[7:0]
IDC2[7:0]
IDC3[7:0]
R/W
R/W
R/W
R/W
0000 0000*
0000 0000*
0000 0000*
0000 0000*
PWM0 Individual Duty Cycle
PWM1 Individual Duty Cycle
PWM2 Individual Duty Cycle
PWM3 Individual Duty Cycle
A 97 kHz ?xed frequency signal is used for each output. Duty cycle is controlled through
256 linear steps from 00h (0 % duty cycle = LED output off) to FFh
(99.6 % duty cycle = LED output at maximum brightness). Applicable to LED outputs
programmed with LDRx = 10 or 11 (LEDOUT register).
IDC [ 7 : 0 ]
duty cycle = ------------------------
256
7.3.4 Group duty cycle control, GRPPWM
Table 11. GRPPWM - Group duty cycle control register (address 06h) bit description
Legend: * default value.
(1)
Address
06h
Register
GRPPWM
Bit
7:0
Symbol
GDC[7:0]
Access
R/W
Value
1111 1111
Description
GRPPWM register
When DMBLNK bit (MODE2 register) is programmed with 0, a 190 Hz ?xed frequency
signal is superimposed with the 97 kHz individual brightness control signal. GRPPWM is
then used as a global brightness control allowing the LED outputs to be dimmed with the
same value. The value in GRPFREQ is then a ‘Don’t care’.
General brightness for the 4 outputs is controlled through 256 linear steps from 00h
(0 % duty cycle = LED output off) to FFh (99.6 % duty cycle = maximum brightness).
Applicable to LED outputs programmed with LDRx = 11 (LEDOUT register).
PCA9633_5
? NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 05 — 25 July 2008
13 of 43
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